Efficient Method for Look-Up-Table Design in Memory Based Fir Filters
نویسنده
چکیده
Distributed arithmetic (DA)-based computation is well known for efficient memory-based implementation of Finite impulse response (FIR) filter where the filter outputs are computed as inner-product of input-sample vectors and filter-coefficient vector. In this paper, we show that the LUT multiplier based approach in which the memory elements store all the possible values of product of filter co-efficient will be the efficient in terms of area with the same throughput in comparison of DA. We present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. The proposed method in this paper have half memory required than the existing DA method .The DA and the proposed LUT method are simulated and synthesized using the Xilinx tool and the memory required by the proposed LUT is nearly 50% lesser than the DA.
منابع مشابه
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed LUT
Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware res...
متن کاملEfficient Hardware Implementation of Digital Filters using Distributed Arithmetic (DA)
The FPGA (Field Programmable Gate Array) constitute of many programmable modules like Configuration Logic Blocks (CLBs), Block Random Access Memories (BRAM), DSP 48 blocks and Input/output (I/O) modules. The CLBs are the main programmable logic units which consist of different number of logic slices and each slice contains different number of LUTs and flips flops depending upon the FPGA device ...
متن کاملDesign and Implementation of 31- Order Fir Low-pass Filter Using Modified Distributed Arithmetic Based on Fpga
This paper provide the principles of Modified Distributed Arithmetic, and introduce it into the FIR filters design, and then presents a 31-order FIR low-pass filter using Modified Distributed Arithmetic, which save considerable MAC blocks to decrease the circuit scale, meanwhile, divided LUT method is used to decrease the required memory units and pipeline structure is also used to increase the...
متن کاملAn Efficient LUT Design on FPGA for Memory-Based Multiplication
An efficient Lookup Table (LUT) design for memory-based multiplier is proposed. This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...
متن کاملHigh Throughput Da-based Fir Filter for Fpga Implementation
In this paper, we present the design optimization of oneand two-dimensional fully-pipelined computing structures for areadelay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the look-up-tab...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2013